1. Field of the Invention
The present invention relates to a direct current cut structure (hereinafter referred to as a DC cut structure) used to connect radio frequency (RF) electronic circuits, more particularly electronic circuits in which a desired frequency characteristic, such as a broadband characteristic which is used in an optical communication system and the like, is required or a variety of RF devices.
2. Description of the Related Art
The DC cut structure is used in RF electronic circuits, more particularly is used in electronic circuits in which a desired frequency characteristic, such as a broad band characteristic which is used in an optical communication system, is required or used in a variety of RF devices, for the connection between them.
If such a DC cut structure is incorporated, for example, between integrated circuits (IC) in an electronic circuit, signals transmitted/received between the ICs can be adjusted to respective required forms by cutting a direct current (DC) element. For example, if in one IC, the input of signals swung around the origin is presumed and in the other IC, the output at a high level or a low level located on one side when seen from the origin, such a DC cut structure is used for the transmission/reception of signals between the ICs.
For capacitors mounted on this DC cut structure, usually a broadband characteristic with the range of several kilohertz to several tens of giga-hertz is required. In order to respond to a request for such a broadband characteristic, in the DC cut structure, generally capacitors each with different capacity are connected in parallel between signal transmission line patters, and a broad band is realized by utilizing the difference in the frequency characteristic between the capacitors.
FIG. 1 shows the respective frequency characteristics of two capacitors used in the DC cut structure. As shown in FIG. 1, a capacitor with large capacity can suppress loss to a low level in a low frequency band, and a capacitor with small capacity can suppress loss to a low level in a high frequency band.
As the parallel connection technology of capacitors, the following several prior arts are known.
Firstly, in the first prior art disclosed in Patent Reference 1, a soldering pattern for disposing a plurality of capacitors on a pattern is provided, and by connecting the plurality of capacitors on the pattern, the parallel connection structure of capacitors is formed.
Next, in the second prior art disclosed in Patent Reference 2, as shown in FIG. 2, an RF micro-chip capacitor 41 with small capacity is connected to one pattern 42, and the other pattern 43 and the electrode unit of the micro-chip capacitor 41 are connected by an Au ribbon 44 or the like. Furthermore, a ceramic capacitor 45 is slantingly inserted between the microchip capacitor 41 and the pattern 42. Thus, the parallel connection structure of capacitors is formed.
In the third prior art disclosed in Patent Reference 3, a capacitor with small capacity is formed by approaching comb-shaped patterns facing each other on one surface of a substrate and another capacitor is provided on the other surface. Thus, the parallel connection structure of capacitors is formed.
Furthermore, in the fourth prior art, as shown in FIG. 3, capacitors 54 and 55 are mounted on the front and rear substrate patterns 51 and 52, respectively, which are connected by a veer 53. Thus, the parallel connection structure of capacitors is formed.
Patent Reference 1: Japanese Patent Laid-open Application No. 6-85511 “Mounting Structure of Broadband Coupler Circuit”
Patent Reference 2: Japanese Patent Laid-open Application No. 5-235602 “Transmission Line”
Patent Reference 3: Japanese Patent Laid-open Application No. 2003-188047 “DC Block Circuit and Communication Equipment”
FIG. 4 shows an equivalent circuit with a DC cut structure.
In such a DC cut structure of FIG. 4, parasitic capacitance due to disposing a capacitor on a pattern in a portion where capacitors are connected in parallel, and parasitic inductance mainly due to a line (for example, Au ribbon 44 shown in FIG. 2) used to connect capacitors occur. Then, in a transmission line whose distributed constant is, for example, 50 ohms, which is the usual application target of such a DC cut structure, these parasitic elements cause impedance mis-matching. As a result, an RF characteristic degrades in such a transmission line, which is a problem.
FIG. 5 shows the simulation results of the influence on an RF characteristic of each parasitic element shown in FIG. 4.
The graph on the right side of FIG. 5 shows the relationship between the frequency (unit: GHz) and loss (unit dB) of a signal traveling through a transmission line pattern at each set value of a parasitic capacitance element (50 fF, 100 fF, 150 fF, 200 fF and 250 fF). It is seen from this right-side graph that in the case of the same parasitic capacitance value, the higher a frequency, the higher loss while in the case of same frequency, the larger a parasitic capacitance value, the higher loss. In other words, when compared in the same structure, the smaller a parasitic capacitance value, the smaller loss.
The graph on the left side of FIG. 5 shows the relationship between the frequency (unit: GHz) and loss (unit dB) of a signal traveling through a transmission line pattern at each set value of a parasitic inductance element (100 pH, 200 pH, 300 pH, 400 pH and 500 pH). It is seen from this left-side graph that in the case of the same parasitic inductance value, the higher a frequency, the higher loss while in the case of same frequency, the larger a parasitic capacitance value, the higher loss. In other words, when compared in the same structure, the smaller a parasitic inductance value, the smaller loss.
The problems of each of the above-mentioned prior arts are listed up below.
In the first prior art, since a parasitic capacitance value increases by disposing a plurality of capacitors on a soldered pattern, an RF characteristic degrades.
In the second prior art, since parasitic inductance occurs due to a line (Au ribbon) 44 used to connect capacitors 41 and 45 and also the parasitic inductance value is essentially proportional to the length of the line, an RF characteristic is restricted according to the line length.
In the third prior art, in order to obtain a sufficient capacitance value as DC cut, the end part of each transmission line pattern must be met each other in the form of a comb of several tens of micrometers by fine processing. Therefore, such fine processing is difficult to make from the viewpoint of processing accuracy.
In the fourth prior art, when connecting the pattern 51 provided on one surface and the pattern 52 provided on the other surface by a veer 53, a band is restricted by the characteristic of the veer 53 and also both-surface wiring around the mounting place of the capacitors 54 and 55 and impedance matching in the veer 53 part are very difficult to make. Therefore, an RF characteristic cannot be secured.
As described above, in order to obtain a good RF characteristic across a broad band while improving the characteristic, each of the above-mentioned parasitic elements (parasitic capacitance and parasitic inductance) must be set low.
In order to obtain a good characteristic in a desired band, for example, across a broad band, it is preferable to be able to easily adjust each parameter, such as line width and the like, in a DC cut structure. In such adjustment, for example, the size of a related place can be modified so as to meet predetermined conditions according to the modification of the line width.
In order to obtain a good characteristic in a desired band, the continuity of the DC cut, for example, the fact that line width can be constant as much as possible, is also important.